Microprocessor Design with Dynamic Clock Source and Multi-Width Instructions

TL;DR

This paper presents a 32-bit RISC-V microprocessor design that employs a dynamic clock source for efficiency and supports both 32-bit and 16-bit compressed instructions, validated through ModelSim simulations.

Contribution

It introduces a novel microprocessor architecture combining dynamic clocking with multi-width instruction support, enhancing efficiency and flexibility.

Findings

Achieved ideal simulation results with ModelSim.

Demonstrated effective operation with both instruction widths.

Improved microprocessor efficiency through dynamic clocking.

Abstract

This paper introduces a novel 32-bit microprocessor, based on the RISC-V instruction set architecture, is designed,utilising a dynamic clock source to achieve high efficiency, overcoming the limitations of hardware delays. In addition, the microprocessor is also aimed to operate with both base (32-bit) instructions and 16-bit compressed instructions. The testing of the design is carried out using ModelSim with an ideal result.