A survey on scheduling and mapping techniques in 3D Network-on-chip

TL;DR

This survey reviews recent research on mapping and scheduling techniques for 3D Network-on-Chip architectures, highlighting methods to optimize communication and performance in multiprocessor systems.

Contribution

It provides a comprehensive classification and analysis of existing mapping and scheduling approaches for 3D NoCs, identifying gaps and future research directions.

Findings

Extensive classification of 3D NoC mapping and scheduling techniques

Identification of key challenges and research gaps

Suggestions for future research directions in 3D NoC optimization

Abstract

Network-on-Chips (NoCs) have been widely employed in the design of multiprocessor system-on-chips (MPSoCs) as a scalable communication solution. NoCs enable communications between on-chip Intellectual Property (IP) cores and allow those cores to achieve higher performance by outsourcing their communication tasks. Mapping and Scheduling methodologies are key elements in assigning application tasks, allocating the tasks to the IPs, and organising communication among them to achieve some specified objectives. The goal of this paper is to present a detailed state-of-the-art of research in the field of mapping and scheduling of applications on 3D NoC, classifying the works based on several dimensions and giving some potential research directions.