3-Dimensional Tuning of an Atomically Defined Silicon Tunnel Junction

TL;DR

This paper demonstrates a 3D epitaxial top-gate technique for silicon tunnel junctions, enabling precise conductance tuning and the implementation of nanoscale logic circuits, advancing quantum device control.

Contribution

It introduces a monolithic 3D epitaxial top-gate for silicon tunnel junctions, significantly improving tunability and enabling complex logic circuit integration.

Findings

Capacitive coupling increased by a factor of 3 with 3D gating

Tunnel barrier height tunable from 0 to 186 meV

Successful implementation of nanoscale AND and OR gates

Abstract

A requirement for quantum information processors is the in-situ tunability of the tunnel rates and the exchange interaction energy within the device. The large energy level separation for atom qubits in silicon is well suited for qubit operation but limits device tunability using in-plane gate architectures, requiring vertically separated top-gates to control tunnelling within the device. In this paper we address control of the simplest tunnelling device in Si:P, the tunnel junction. Here we demonstrate that we can tune its conductance by using a vertically separated top-gate aligned with +-5nm precision to the junction. We show that a monolithic 3D epitaxial top-gate increases the capacitive coupling by a factor of 3 compared to in-plane gates, resulting in a tunnel barrier height tunability of 0-186meV. By combining multiple gated junctions in series we extend our monolithic 3D gating technology to implement nanoscale logic circuits including AND and OR gates.