Hardware/Software co-design with ADC-Less In-memory Computing Hardware for Spiking Neural Networks
Marco Paul E. Apolinario, Adarsh Kumar Kosta, Utkarsh Saxena, Kaushik, Roy

TL;DR
This paper presents a hardware/software co-design approach for deploying Spiking Neural Networks on ADC-Less In-Memory Computing hardware, significantly reducing energy and latency while maintaining accuracy.
Contribution
It introduces an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs and a hardware-aware training method to minimize accuracy loss.
Findings
Achieves 2-7x energy reduction compared to HP-ADC IMC.
Reduces latency by 8.9-24.6x depending on workload.
Enables complex sequential tasks like optical flow and gesture recognition.
Abstract
Spiking Neural Networks (SNNs) are bio-plausible models that hold great potential for realizing energy-efficient implementations of sequential tasks on resource-constrained edge devices. However, commercial edge platforms based on standard GPUs are not optimized to deploy SNNs, resulting in high energy and latency. While analog In-Memory Computing (IMC) platforms can serve as energy-efficient inference engines, they are accursed by the immense energy, latency, and area requirements of high-precision ADCs (HP-ADC), overshadowing the benefits of in-memory computations. We propose a hardware/software co-design methodology to deploy SNNs into an ADC-Less IMC architecture using sense-amplifiers as 1-bit ADCs replacing conventional HP-ADCs and alleviating the above issues. Our proposed framework incurs minimal accuracy degradation by performing hardware-aware training and is able to scale…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Neural Networks and Reservoir Computing · Neural dynamics and brain function
