Implementation of the Digital QS-SVM-based Beamformer on an FPGA Platform

TL;DR

This paper presents an FPGA implementation of a digital beamformer using QS-SVM for DOA estimation, enhancing signal suppression and performance in 10 GHz wireless systems.

Contribution

It introduces a novel FPGA deployment of a QS-SVM-based beamformer with improved DOA estimation and signal suppression capabilities.

Findings

Achieved deep nulls less than -10 dB for undesired signals.

Demonstrated over 90% performance efficiency.

Latency in the order of milliseconds with 100% throughput.

Abstract

To address practical challenges in establishing and maintaining robust wireless connectivity such as multi-path effects, low latency, size reduction, and high data rate, the digital beamformer is performed by the hybrid antenna array at the frequency of operation of 10 GHz. The proposed digital beamformer, as a spatial filter, is capable of performing Direction of Arrival (DOA) estimation and beamforming. The most well-established machine learning technique of support vector machine (SVM) for the DoA estimation is limited to problems with linearly-separable datasets. To overcome the aforementioned constraint, in the proposed beamformer, the QS-SVM classifier with a small regularizer has been used for the DoA estimation in addition to the two beamforming techniques of LCMV and MVDR. The QS-SVM-based beamformer has been deployed in an FPGA board, as demonstrated in detail in this work. The implementation results have verified the strong performance of the QS-SVM-based beamformer in suppressing undesired signals, deep nulls with powers less than -10 dB in undesired signals, and transferring desired signals. Furthermore, we have demonstrated that the performance of the QS-SVM-based beamformer consists of other advantages of average latency time in the order of milliseconds, performance efficiency of more than 90\%, and throughput of about 100\%.