Integrated Photonic Tensor Processing Unit for a Matrix Multiply: a Review

TL;DR

This review discusses the potential of integrated photonic tensor processing units for matrix multiplication, emphasizing their advantages over electronic counterparts and exploring future challenges in photonic neural network accelerators.

Contribution

It provides a comprehensive overview of photonic hardware architectures for neural network acceleration, comparing linear and nonlinear components on integrated photonic circuits.

Findings

Photonic accelerators offer high bandwidth and low energy consumption.

Current architectures demonstrate promising performance for neural network tasks.

Main challenges include integration complexity and scalability.

Abstract

The explosion of artificial intelligence and machine-learning algorithms, connected to the exponential growth of the exchanged data, is driving a search for novel application-specific hardware accelerators. Among the many, the photonics field appears to be in the perfect spotlight for this global data explosion, thanks to its almost infinite bandwidth capacity associated with limited energy consumption. In this review, we will overview the major advantages that photonics has over electronics for hardware accelerators, followed by a comparison between the major architectures implemented on Photonics Integrated Circuits (PIC) for both the linear and nonlinear parts of Neural Networks. By the end, we will highlight the main driving forces for the next generation of photonic accelerators, as well as the main limits that must be overcome.