Stochastic thermodynamic bounds on logical circuit operation

TL;DR

This paper investigates thermodynamic limits on logical circuit operations using a mesoscopic model, revealing trade-offs between heat dissipation, operation certainty, and memory retention, with implications for thermodynamically optimized computing.

Contribution

It introduces a thermodynamically consistent model for CMOS circuits and explores fundamental bounds on their operation near thermal energies, highlighting control mechanisms for optimal performance.

Findings

Direction-dependent dynamics in NOT gates.

Exponential relationship between memory time and energy.

Maximized cycle time certainty near thermal biasing.

Abstract

Using a thermodynamically consistent, mesoscopic model for modern complementary metal-oxide-semiconductor transistors, we study an array of logical circuits and explore how their function is constrained by recent thermodynamic uncertainty relations when operating near thermal energies. For a single NOT gate, we find operating direction-dependent dynamics, and a trade-off between dissipated heat and operation time certainty. For a memory storage device, we find an exponential relationship between the memory retention time and energy required to sustain that memory state. For a clock, we find that the certainty in the cycle time is maximized at biasing voltages near thermal energy, as is the trade-off between this certainty and the heat dissipated per cycle. We identify a control mechanism that can increase the cycle time certainty without an offsetting increase in heat dissipation by working at a resonance condition for the clock. These results provide a framework for assessing thermodynamic costs of realistic computing devices, allowing for circuits to be designed and controlled for thermodynamically optimal operation.