Reliability-Aware Deployment of DNNs on In-Memory Analog Computing Architectures

TL;DR

This paper proposes a reliability-aware method for deploying large DNN matrices on multiple smaller in-memory analog computing subarrays, reducing noise and parasitic effects while maintaining energy-efficient analog domain computation.

Contribution

It introduces a practical deployment strategy for large DNN matrices on multiple IMAC subarrays to enhance reliability and energy efficiency.

Findings

Reduces noise and parasitic effects in analog DNN computations.

Maintains high energy efficiency by avoiding digital signal conversion.

Improves reliability of in-memory analog computing architectures.

Abstract

Conventional in-memory computing (IMC) architectures consist of analog memristive crossbars to accelerate matrix-vector multiplication (MVM), and digital functional units to realize nonlinear vector (NLV) operations in deep neural networks (DNNs). These designs, however, require energy-hungry signal conversion units which can dissipate more than 95% of the total power of the system. In-Memory Analog Computing (IMAC) circuits, on the other hand, remove the need for signal converters by realizing both MVM and NLV operations in the analog domain leading to significant energy savings. However, they are more susceptible to reliability challenges such as interconnect parasitic and noise. Here, we introduce a practical approach to deploy large matrices in DNNs onto multiple smaller IMAC subarrays to alleviate the impacts of noise and parasitics while keeping the computation in the analog domain.