Enabling Atomic Durability for Persistent Memory with Transiently Persistent CPU Cache
Chongnan Ye, Meng Chen, Qisheng Jiang, Chundong Wang

TL;DR
This paper introduces Hercules, a hardware logging system that leverages CPU cache with eADR support to achieve atomic durability in persistent memory, improving throughput and reducing pmem writes.
Contribution
Hercules enables atomic durability using CPU cache as a redo log with minimal pmem writes, a novel hardware design for persistent memory systems.
Findings
Hercules achieves higher throughput than existing solutions.
It significantly reduces pmem write operations.
The system ensures crash consistency with efficient recovery.
Abstract
Persistent memory (pmem) products bring the persistence domain up to the memory level. Intel recently introduced the eADR feature that guarantees to flush data buffered in CPU cache to pmem on a power outage, thereby making the CPU cache a transient persistence domain. Researchers have explored how to enable the atomic durability for applications' in-pmem data. In this paper, we exploit the eADR-supported CPU cache to do so. A modified cache line, until written back to pmem, is a natural redo log copy of the in-pmem data. However, a write-back due to cache replacement or eADR on a crash overwrites the original copy. We accordingly develop Hercules, a hardware logging design for the transaction-level atomic durability, with supportive components installed in CPU cache, memory controller (MC), and pmem. When a transaction commits, Hercules commits on-chip its data staying in cache lines.…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · Parallel Computing and Optimization Techniques · Advanced Data Storage Technologies
