Signatures of gate-driven out of equilibrium superconductivity in Ta/InAs nanowires

TL;DR

This study reveals that gate-controlled supercurrent suppression in Ta/InAs nanowires is primarily caused by gate leakage power dissipation, with high-energy fluctuations inducing multiple phase slips, advancing understanding of superconducting switching mechanisms.

Contribution

It demonstrates that gate leakage power, not electrostatic effects, governs supercurrent suppression in Ta/InAs nanowires, clarifying the microscopic origin of gate-controlled superconductivity.

Findings

Gate leakage power determines supercurrent suppression.

High-energy fluctuations cause multiple phase slips.

Gate influence differs from temperature effects on supercurrent.

Abstract

Understanding the microscopic origin of the gate-controlled supercurrent (GCS) in superconducting nanobridges is crucial for engineering superconducting switches suitable for a variety of electronic applications. The origin of GCS is controversial, and various mechanisms have been proposed to explain it. In this work, we have investigated the GCS in a Ta layer deposited on the surface of InAs nanowires. Comparison between switching current distributions at opposite gate polarities and between the gate dependence of two opposite side gates with different nanowire$-$gate spacings shows that the GCS is determined by the power dissipated by the gate leakage. We also found a substantial difference between the influence of the gate and elevated bath temperature on the magnetic field dependence of the supercurrent. Detailed analysis of the switching dynamics at high gate voltages shows that the device is driven into the multiple phase slips regime by high-energy fluctuations arising from the leakage current.