Tuning the conductance topology in solids

TL;DR

This paper provides a microscopic analytical framework to understand and tune the conductance topology in solids, linking hysteresis and memory effects to microscopic trapping phenomena and intrinsic material features.

Contribution

It introduces a novel analytical solution that characterizes current-voltage hysteresis as a modulation of conductance topology, aiding in understanding transport and electrochemical properties.

Findings

Memory effects linked to trapping sites and symmetry constraints.

Simplification of complex impedance and voltammetry data.

Identification of intrinsic features affecting electronic transport.

Abstract

The inertia of trapping and detrapping of nonequilibrium charge carriers affects the electrochemical and transport properties of both bulk and nanoscopic structures in a very peculiar way. An emerging memory response with a hysteresis in the current-voltage response and its eventual multiple crossing, produced by this universally available ingredient, are signatures of this process. Here, we deliver a microscopic and analytical solution for these behaviors, understood as the modulation of the topology of the current-voltage loops. The memory emergence becomes thus a characterization tool for intrinsic features that affect the electronic transport of solids such as the nature and number of trapping sites, intrinsic symmetry constraints, and natural relaxation time scales. This method is also able to reduce the seeming complexity of frequency-dependent electrochemical impedance and cyclic voltammetry observable for a variety of systems to a combination of simple microscopic ingredients.