An Investigation into Neuromorphic ICs using Memristor-CMOS Hybrid Circuits
Udit Kumar Agarwal, Shikhar Makhija, Varun Tripathi, Kunwar Singh

TL;DR
This paper explores the design and simulation of memristor-CMOS hybrid circuits for neuromorphic computing, focusing on building blocks for neural networks and convolutional layers to enhance parallel processing and non-linear functions.
Contribution
It introduces novel memristor-based circuit blocks for synaptic weighting, activation functions, and CNN layers, advancing neuromorphic hardware design.
Findings
Successful simulation of memristor-based synaptic and activation blocks
Design of a convolutional layer for image processing applications
Validation of circuit performance through neural network implementation
Abstract
The memristance of a memristor depends on the amount of charge flowing through it and when current stops flowing through it, it remembers the state. Thus, memristors are extremely suited for implementation of memory units. Memristors find great application in neuromorphic circuits as it is possible to couple memory and processing, compared to traditional Von-Neumann digital architectures where memory and processing are separate. Neural networks have a layered structure where information passes from one layer to another and each of these layers have the possibility of a high degree of parallelism. CMOS-Memristor based neural network accelerators provide a method of speeding up neural networks by making use of this parallelism and analog computation. In this project we have conducted an initial investigation into the current state of the art implementation of memristor based programming…
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Taxonomy
TopicsAdvanced Memory and Neural Computing · CCD and CMOS Imaging Sensors · Neural Networks and Applications
MethodsTest
