Design and development of the ALICE common readout unit user logic firmware for the Muon Identifier readout chain

TL;DR

This paper presents the design and development of FPGA firmware for the ALICE Muon Identifier readout system, enabling efficient processing of increased data rates after the LHC upgrade.

Contribution

It introduces a novel FPGA firmware approach for the Muon Identifier readout chain to handle higher data volumes post-upgrade.

Findings

Successful implementation of FPGA firmware for data processing

Enhanced data handling capacity for the Muon Identifier

Supports triggerless continuous readout mode

Abstract

A Large Ion Collider Experiment (ALICE) at the Large Hadron Collider (LHC) at CERN went through a major upgrade in which some of its subdetectors were replaced with new ones, while others are equipped with new electronics. The aim of the upgrade is to withstand higher collision rates during the third running period (Run 3), which started in 2022. As part of the upgrade, certain subdetectors such as the Muon Trigger, renamed to Muon Identifier, now operate in a continuous, triggerless readout mode, in addition to the previous triggered readout mode. Due to the increased quantity of data, typical methodologies are impossible to employ without massive efforts to expand the processing capacity. Since the new ALICE computing system cannot keep up with the increased data flow of the Muon Identifier, a new processing algorithm has been established. These proceedings provide a insight to the new approach of processing the Muon Identifier readout data based on a customized user logic FPGA firmware.