Pipelined Architecture for Soft-decision Iterative Projection Aggregation Decoding for RM Codes

TL;DR

This paper introduces a flexible hardware architecture for the iterative projection-aggregation (IPA) decoding of Reed-Muller codes, achieving significant improvements in throughput and area efficiency over existing decoders.

Contribution

It presents a configurable hardware design for IPA decoding that balances resource use and performance, enabling practical implementation for various applications.

Findings

41% lower area consumption compared to SCL decoder

44% lower latency and four times higher throughput

Seven times higher power consumption for the same code length

Abstract

The recently proposed recursive projection-aggregation (RPA) decoding algorithm for Reed-Muller codes has received significant attention as it provides near-ML decoding performance at reasonable complexity for short codes. However, its complicated structure makes it unsuitable for hardware implementation. Iterative projection-aggregation (IPA) decoding is a modified version of RPA decoding that simplifies the hardware implementation. In this work, we present a flexible hardware architecture for the IPA decoder that can be configured from fully-sequential to fully-parallel, thus making it suitable for a wide range of applications with different constraints and resource budgets. Our simulation and implementation results show that the IPA decoder has 41% lower area consumption, 44% lower latency, four times higher throughput, but currently seven times higher power consumption for a code with block length of 128 and information length of 29 compared to a state-of-the-art polar successive cancellation list (SCL) decoder with comparable decoding performance.