Gradient Backpropagation based Feature Attribution to Enable Explainable-AI on the Edge
Ashwin Bhat, Adou Sangbone Assoa, Arijit Raychowdhury

TL;DR
This paper presents a flexible FPGA-based hardware design for gradient backpropagation feature attribution algorithms, enabling real-time explainable AI on edge devices with minimal resource overhead.
Contribution
It analyzes dataflow and optimizes gradient computation for feature attribution, developing a configurable FPGA design supporting multiple algorithms for edge deployment.
Findings
Supports three feature attribution algorithms on FPGA
Demonstrates real-time performance on Xilinx FPGAs
Uses 16-bit fixed-point precision for CNN inference
Abstract
There has been a recent surge in the field of Explainable AI (XAI) which tackles the problem of providing insights into the behavior of black-box machine learning models. Within this field, \textit{feature attribution} encompasses methods which assign relevance scores to input features and visualize them as a heatmap. Designing flexible accelerators for multiple such algorithms is challenging since the hardware mapping of these algorithms has not been studied yet. In this work, we first analyze the dataflow of gradient backpropagation based feature attribution algorithms to determine the resource overhead required over inference. The gradient computation is optimized to minimize the memory overhead. Second, we develop a High-Level Synthesis (HLS) based configurable FPGA design that is targeted for edge devices and supports three feature attribution algorithms. Tile based computation is…
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Taxonomy
TopicsGenerative Adversarial Networks and Image Synthesis · Advanced Neural Network Applications · Explainable Artificial Intelligence (XAI)
