First Test Results of the Trans-Impedance Amplifier Stage of the Ultra-fast HPSoC ASIC

TL;DR

This paper reports initial test results of a high-speed ASIC designed for reading out ultra-fast silicon detectors, demonstrating promising timing performance but also identifying areas for improvement in gain and jitter.

Contribution

It introduces the first test results of a 65 nm CMOS ASIC optimized for ultra-fast silicon detector readout, highlighting its performance and ongoing design improvements.

Findings

Fast output rise time of 600 ps confirmed

Timing jitter measured at 45 ps

Gain limitations identified for further optimization

Abstract

We present the first results from the HPSoC ASIC designed for readout of Ultra-fast Silicon Detectors. The 4-channel ASIC manufactured in 65 nm CMOS by TSMC has been optimized for 50 um thick AC-LGAD. The evaluation of the analog front end with \b{eta}-particles impinging on 3x3 AC-LGAD arrays (500 um pitch, 200x200 um2 metal) confirms a fast output rise time of 600 ps and good timing performance with a jitter of 45 ps. Further calibration experiments and TCT laser studies indicate some gain limitations that are being investigated and are driving the design of the second-generation pre-amplification stages to reach a jitter of 15 ps.