PaST-NoC: A Packet-Switched Superconducting Temporal NoC

TL;DR

This paper introduces PaST-NoC, a scalable, area-efficient superconducting network on chip that uses temporal domain control and race logic to significantly improve throughput per area over existing superconducting binary NoCs.

Contribution

It proposes a novel packet-switched superconducting temporal NoC design utilizing race logic and bufferless flow control, enabling scalable topologies and enhanced performance.

Findings

Outperforms state-of-the-art superconducting binary NoCs in throughput per area by up to 5x for long packets.

Demonstrates scalability to arbitrary topologies based on 2x2 routers and 4x4 butterfly networks.

Uses race logic for control path, reducing area and power overheads.

Abstract

Temporal computing promises to mitigate the stringent area constraints and clock distribution overheads of traditional superconducting digital computing. To design a scalable, area- and power-efficient superconducting network on chip (NoC), we propose packet-switched superconducting temporal NoC (PaST-NoC). PaST-NoC operates its control path in the temporal domain using race logic (RL), combined with bufferless deflection flow control to minimize area. Packets encode their destination using RL and carry a collection of data pulses that the receiver can interpret as pulse trains, RL, serialized binary, or other formats. We demonstrate how to scale up PaST-NoC to arbitrary topologies based on 2x2 routers and 4x4 butterflies as building blocks. As we show, if data pulses are interpreted using RL, PaST-NoC outperforms state-of-the-art superconducting binary NoCs in throughput per area by as much as 5x for long packets.