FPGA Hardware Acceleration for Feature-Based Relative Navigation Applications

TL;DR

This paper presents an FPGA-based embedded architecture that accelerates feature-based relative pose estimation between point clouds for real-time vision navigation, achieving high speed with low numerical error.

Contribution

It develops a hardware/software co-design implementing a finite-precision OLTAE algorithm on FPGA for fast, resource-efficient pose estimation in constrained environments.

Findings

FPGA implementation achieves high-speed pose estimation.

Numerical errors are kept below 7%.

Demonstrates suitability for real-time navigation applications.

Abstract

Estimation of rigid transformation between two point clouds is a computationally challenging problem in vision-based relative navigation. Targeting a real-time navigation solution utilizing point-cloud and image registration algorithms, this paper develops high-performance avionics for power and resource constrained pose estimation framework. A Field-Programmable Gate Array (FPGA) based embedded architecture is developed to accelerate estimation of relative pose between the point-clouds, aided by image features that correspond to the individual point sets. At algorithmic level, the pose estimation method is an adaptation of Optimal Linear Attitude and Translation Estimator (OLTAE) for relative attitude and translation estimation. At the architecture level, the proposed embedded solution is a hardware/software co-design that evaluates the OLTAE computations on the bare-metal hardware for high-speed state estimation. The finite precision FPGA evaluation of the OLTAE algorithm is compared with a double-precision evaluation on MATLAB for performance analysis and error quantification. Implementation results of the proposed finite-precision OLTAE accelerator demonstrate the high-performance compute capabilities of the FPGA-based pose estimation while offering relative numerical errors below 7%.