A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design

TL;DR

This paper introduces an open-source RISC-V V 1.0 vector processor design, demonstrating its efficient architecture and performance advantages over previous versions, suitable for data-parallel workloads.

Contribution

It presents the first open-source implementation of RISC-V V 1.0 vector extension, analyzing its impact on micro-architecture and performance optimization.

Findings

15% better area efficiency compared to older vector engines

6% improved throughput over state-of-the-art designs

FPU utilization exceeds 98.5% on key kernels

Abstract

Vector architectures are gaining traction for highly efficient processing of data-parallel workloads, driven by all major ISAs (RISC-V, Arm, Intel), and boosted by landmark chips, like the Arm SVE-based Fujitsu A64FX, powering the TOP500 leader Fugaku. The RISC-V V extension has recently reached 1.0-Frozen status. Here, we present its first open-source implementation, discuss the new specification's impact on the micro-architecture of a lane-based design, and provide insights on performance-oriented design of coupled scalar-vector processors. Our system achieves comparable/better PPA than state-of-the-art vector engines that implement older RVV versions: 15% better area, 6% improved throughput, and FPU utilization >98.5% on crucial kernels.