Radiation studies performed on the High Luminosity ATLAS TileCal link Daughterboard

TL;DR

This paper reports on radiation qualification tests and performance evaluations of the Daughterboard used in the HL-LHC ATLAS TileCal upgrade, focusing on its radiation resilience and reliability.

Contribution

It provides an updated summary of TID, NIEL, and SEE tests, and performance studies for the Daughterboard revision 6 design, highlighting radiation mitigation strategies.

Findings

Daughterboard demonstrates robust radiation tolerance.

Redundant design effectively mitigates single points of failure.

Performance remains stable under radiation testing conditions.

Abstract

The new electronics of the ATLAS Tile Calorimeter for the HL-LHC interfaces the on-detector and off-detector electronics by means of a Daughterboard. The Daughterboard is positioned on-detector featuring commercial SFPs+, CERN GBTx ASICs, ProASIC FPGAs and Kintex Ultrascale FPGAs. The design minimizes single points of failure and mitigates radiation damage by means of a double redundant scheme, Triple Mode Redundancy, Xilinx Soft Error Mitigation IP, CRC/FEC for link data transfer, and SEL protection circuitry. We present an updated summary of the TID, NIEL and SEE qualification tests, and performance studies of the Daughterboard revision 6 design.