Towards Dynamic Fault Tolerance for Hardware-Implemented Artificial Neural Networks: A Deep Learning Approach
Daniel Gregorek, Nils H\"ulsmeier, Steffen Paul

TL;DR
This paper proposes a deep learning-based method to enhance fault tolerance in hardware-implemented neural networks, demonstrating improved robustness and reduced test loss under fault conditions without extra hardware.
Contribution
It introduces a novel deep learning approach for dynamic fault mitigation in neural networks, showing effectiveness in fault tolerance and loss reduction.
Findings
Over 2% reduction in test loss with sufficient training epochs.
Linear relationship between test loss and fault injection rate.
Improved performance even without faults during testing.
Abstract
The functionality of electronic circuits can be seriously impaired by the occurrence of dynamic hardware faults. Particularly, for digital ultra low-power systems, a reduced safety margin can increase the probability of dynamic failures. This work investigates a deep learning approach to mitigate dynamic fault impact for artificial neural networks. As a theoretic use case, image compression by means of a deep autoencoder is considered. The evaluation shows a linear dependency of the test loss to the fault injection rate during testing. If the number of training epochs is sufficiently large, our approach shows more than 2% reduction of the test loss compared to a baseline network without the need of additional hardware. At the absence of faults during testing, our approach also decreases the test loss compared to reference networks.
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Taxonomy
TopicsAdvancements in Semiconductor Devices and Circuit Design · Radiation Effects in Electronics · Integrated Circuits and Semiconductor Failure Analysis
MethodsTest
