Process Yield and Device Stability Improvement for Sol-gel Alumina Passivation layer based GFETs

TL;DR

This study demonstrates that using a 0.05 M sol-gel alumina passivation layer significantly improves the process yield and stability of GFET devices compared to 0.1 M, providing a low-cost, low-temperature solution for reliable device fabrication.

Contribution

The paper introduces an optimized sol-gel alumina passivation process that enhances GFET stability and process yield, addressing stability issues with a simple, low-cost method.

Findings

0.05 M alumina yields 100% process success and stable operation over two months.

0.1 M alumina causes cracking and rapid device degradation.

Optimized process recipe improves GFET reliability and manufacturing yield.

Abstract

The stability of GFET devices is a major problem and needs a good passivation layer for the same. Low cost and low-temperature sol-gel alumina passivation layer-based GFETs is studied here with the goals to improve stability of the device and achieve high process yield. The process yield and device stability are explored for two different molarities of 0.1 M and 0.05 M. The parameters like mobility, trap charge density, minimum conductivity plateau width and minimum conductivity are extracted to compare the stability of devices. The results indicate that GFETs with 0.1 M have problems of process yield due to crack formation in the channel region post-annealing, where close to half of the devices are working, and also working devices are are not stable and degrading very fast within a week's time. On the other hand, 0.05 M sol-gel Alumina-based sample exhibits 100$\%$ process yield with all working devices and observed stable behavior for more than two months. Hence we propose an optimized process recipe for a sol-gel Alumina-based passivation layer to achieve the best possible process yield and device stability for GFETs.