A Near-Sensor Processing Accelerator for Approximate Local Binary Pattern Networks

TL;DR

This paper introduces a high-speed, energy-efficient near-sensor accelerator for Local Binary Pattern networks, combining approximate hardware design with in-memory processing to significantly reduce power consumption and execution time.

Contribution

It presents a novel Ap-LBP network and NS-LBP architecture that enable efficient, multiply-accumulate-free feature extraction and processing near the sensor, reducing data transmission energy.

Findings

Achieves 1.25 GHz processing speed and 37.4 TOPS/W energy efficiency.

Reduces energy consumption by 2.2x compared to recent LBP networks.

Speeds up execution time by 4x over existing LBP-based methods.

Abstract

In this work, a high-speed and energy-efficient comparator-based Near-Sensor Local Binary Pattern accelerator architecture (NS-LBP) is proposed to execute a novel local binary pattern deep neural network. First, inspired by recent LBP networks, we design an approximate, hardware-oriented, and multiply-accumulate (MAC)-free network named Ap-LBP for efficient feature extraction, further reducing the computation complexity. Then, we develop NS-LBP as a processing-in-SRAM unit and a parallel in-memory LBP algorithm to process images near the sensor in a cache, remarkably reducing the power consumption of data transmission to an off-chip processor. Our circuit-to-application co-simulation results on MNIST and SVHN data-sets demonstrate minor accuracy degradation compared to baseline CNN and LBP-network models, while NS-LBP achieves 1.25 GHz and energy-efficiency of 37.4 TOPS/W. NS-LBP reduces energy consumption by 2.2x and execution time by a factor of 4x compared to the best recent LBP-based networks.