Seed Layer Engineering for Crack-free Sol-gel Alumina Deposition on GFETs

TL;DR

This paper presents a novel seed layer engineering approach combined with DUV annealing to prevent cracks in sol-gel alumina dielectric layers on GFETs, enabling low-cost, low-temperature fabrication with preserved electrical properties.

Contribution

A new two-step seed layer deposition method with DUV annealing is introduced to eliminate cracks in sol-gel alumina on GFETs, improving fabrication reliability.

Findings

Cracks are caused by TEC mismatch and solvent shrinkage stress.

The proposed two-step seed layer with DUV annealing effectively prevents cracks.

Electrical performance, including the Dirac point, is maintained after treatment.

Abstract

Low cost and low thermal budget based spin-coated sol-gel Alumina was explored as a dielectric/passivation layer for GFET. Post thermal annealing, the crack was observed in sol-gel Alumina layer exactly above the graphene channel. The possible mechanism of crack could be graphene lateral restoring movement due to (i) Thermal Expansion Coefficient (TEC) difference between graphene and adjacent layers and (ii) shrinkage stress generated during the solvent removal process. Based on the crack formation phenomenon, a combination of different annealing schemes (low thermal budget DUV annealing) and seed layer engineering (thickness and different deposition schemes) were carried out. Finally, a novel two-step seed layer deposition method with DUV annealing was proposed and demonstrated to resolve the crack issue successfully and also able to retain the Dirac point in the electrical characteristics.