Temporal Vectorization: A Compiler Approach to Automatic Multi-Pumping

TL;DR

This paper introduces a compiler-based approach called Temporal Vectorization that automates multi-pumping in FPGA designs, enabling higher clock frequencies and resource efficiency through data movement analysis at the high-level programming stage.

Contribution

It presents a novel compiler optimization framework that automatically applies multi-pumping by leveraging multiple clock domains, reducing resource use and enhancing performance in FPGA designs.

Findings

Resource consumption reduced by up to 50%

Average resource reduction of 23%

Enables higher parallelism and performance in scalable designs

Abstract

The multi-pumping resource sharing technique can overcome the limitations commonly found in single-clocked FPGA designs by allowing hardware components to operate at a higher clock frequency than the surrounding system. However, this optimization cannot be expressed in high levels of abstraction, such as HLS, requiring the use of hand-optimized RTL. In this paper we show how to leverage multiple clock domains for computational subdomains on reconfigurable devices through data movement analysis on high-level programs. We offer a novel view on multi-pumping as a compiler optimization - a superclass of traditional vectorization. As multiple data elements are fed and consumed, the computations are packed temporally rather than spatially. The optimization is applied automatically using an intermediate representation that maps high-level code to HLS. Internally, the optimization injects modules into the generated designs, incorporating RTL for fine-grained control over the clock domains. We obtain a reduction of resource consumption by up to 50% on critical components and 23% on average. For scalable designs, this can enable further parallelism, increasing overall performance.