Benchmarking multi-qubit gates -- I: Metrological aspects
Bharath Hebbe Madhusudhana

TL;DR
This paper introduces a new figure-of-merit for benchmarking multi-qubit gates in quantum computing, focusing on the reduced Choi matrix and developing scalable, metrologically enhanced protocols to improve characterization efficiency.
Contribution
It develops a scalable protocol for complete characterization of the reduced Choi matrix and introduces metrological techniques using quantum information scrambling and entanglement to speed up sampling convergence.
Findings
Fundamental limits to sampling error convergence rates identified.
Protocols using quantum scrambling improve convergence speed.
Entangled states enhance measurement precision.
Abstract
Accurate and precise control of large quantum systems is paramount to achieve practical advantages on quantum devices. Therefore, benchmarking the hardware errors in quantum computers has drawn significant attention lately. Existing benchmarks for digital quantum computers involve averaging the global fidelity over a large set of quantum circuits and are therefore unsuitable for specific multi-qubit gates used in analog quantum operations. Moreover, average global fidelity is not the optimal figure-of-merit for some of the applications specific to multi-qubit gates and analog devices , such as the study of many-body physics, which often use local observables. In this two-part paper, we develop a new figure-of-merit suitable for multi-qubit quantum gates based on the reduced Choi matrix of the operation. In the first part, we develop an efficient, scalable protocol to completely…
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Taxonomy
TopicsQuantum Computing Algorithms and Architecture · Quantum Information and Cryptography · Advancements in Semiconductor Devices and Circuit Design
