Low Error-Rate Approximate Multiplier Design for DNNs with Hardware-Driven Co-Optimization

TL;DR

This paper introduces low-error approximate multipliers optimized for DNN hardware, reducing area and power while maintaining accuracy through co-optimization and retraining.

Contribution

It proposes novel approximate 3x3 multipliers with significant area and power savings, integrated into larger multipliers for DNNs with a hardware-software co-optimization approach.

Findings

Reduced area by up to 36% compared to exact multipliers

Power consumption decreased by approximately 36%

Achieved higher accuracy than other approximate multipliers on public datasets

Abstract

In this paper, two approximate 3*3 multipliers are proposed and the synthesis results of the ASAP-7nm process library justify that they can reduce the area by 31.38% and 36.17%, and the power consumption by 36.73% and 35.66% compared with the exact multiplier, respectively. They can be aggregated with a 2*2 multiplier to produce an 8*8 multiplier with low error rate based on the distribution of DNN weights. We propose a hardware-driven software co-optimization method to improve the DNN accuracy by retraining. Based on the proposed two approximate 3-bit multipliers, three approximate 8-bit multipliers with low error-rate are designed for DNNs. Compared with the exact 8-bit unsigned multiplier, our design can achieve a significant advantage over other approximate multipliers on the public dataset.