PeF: Poisson's Equation Based Large-Scale Fixed-Outline Floorplanning

TL;DR

This paper introduces a novel Poisson's equation-based mathematical model for large-scale fixed-outline floorplanning in VLSI design, improving wirelength and efficiency over existing methods.

Contribution

It presents a new mathematical model and an algorithm that integrates global floorplanning with legalization, optimizing module placement using Poisson's equation.

Findings

Improves average wirelength by at least 2% on small benchmarks.

Achieves at least 5% wirelength reduction on large benchmarks.

Demonstrates effectiveness on multiple benchmark datasets.

Abstract

Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine definitely has positive impact on chip design speed, quality and performance. In this paper, we present a novel mathematical model to characterize non-overlapping of modules, and propose a flat fixed-outline floorplanning algorithm based on the VLSI global placement approach using Poisson's equation. The algorithm consists of global floorplanning and legalization phases. In global floorplanning, we redefine the potential energy of each module based on the novel mathematical model for characterizing non-overlapping of modules and an analytical solution of Poisson's equation. In this scheme, the widths of soft modules appear as variables in the energy function and can be optimized. Moreover, we design a fast approximate computation scheme for partial derivatives of the potential energy. In legalization, based on the defined horizontal and vertical constraint graphs, we eliminate overlaps between modules remained after global floorplanning, by modifying relative positions of modules. Experiments on the MCNC, GSRC, HB+ and ami49\_x benchmarks show that, our algorithm improves the average wirelength by at least 2\% and 5\% on small and large scale benchmarks with certain whitespace, respectively, compared to state-of-the-art floorplanners.