Towards the Multiple Constant Multiplication at Minimal Hardware Cost

TL;DR

This paper presents an improved ILP-based approach for Multiple Constant Multiplication that minimizes hardware cost by considering one-bit adder counts, intermediate truncations, and error bounds, resulting in more efficient multiplierless circuits.

Contribution

It introduces a new hardware cost model based on one-bit adders, incorporates error bounds into ILP, and provides an open-source tool integrated with FloPoCo for optimized MCM circuit design.

Findings

The new cost model correlates strongly with LUT count.

Intermediate truncations significantly reduce resource usage.

The approach guarantees user-defined error bounds in MCM circuits.

Abstract

Multiple Constant Multiplication (MCM) over integers is a frequent operation arising in embedded systems that require highly optimized hardware. An efficient way is to replace costly generic multiplication by bit-shifts and additions, i.e. a multiplierless circuit. In this work, we improve the state-of-the-art optimal approach for MCM, based on Integer Linear Programming (ILP). We introduce a new lower-level hardware cost, based on counting the number of one-bit adders and demonstrate that it is strongly correlated with the LUT count. This new model for the multiplierless MCM circuits permitted us to consider intermediate truncations that permit to significantly save resources when a full output precision is not required. We incorporate the error propagation rules into our ILP model to guarantee a user-given error bound on the MCM results. The proposed ILP models for multiple flavors of MCM are implemented as an open-source tool and, combined with the FloPoCo code generator, provide a complete coefficient-to-VHDL flow. We evaluate our models in extensive experiments, and propose an in-depth analysis of the impact that design metrics have on actually synthesized hardware.