Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing

TL;DR

This paper evaluates the performance of modern System-on-Chip architectures for quantum control of trapped-ion qubits, focusing on data transfer latency and throughput to enable fast gate reconfiguration within quantum systems.

Contribution

It provides an analysis of high-speed on-chip communication mechanisms, especially DMA, demonstrating their suitability for real-time quantum gate control in SoC-based systems.

Findings

DMA achieves up to 19.2 GB/s bandwidth

Gate reconfiguration can be done in less than 2 microseconds

Communication rates are applicable across various quantum technologies

Abstract

Electronic control systems used for quantum computing have become increasingly complex as multiple qubit technologies employ larger numbers of qubits with higher fidelity targets. Whereas the control systems for different technologies share some similarities, parameters like pulse duration, throughput, real-time feedback, and latency requirements vary widely depending on the qubit type. In this paper, we evaluate the performance of modern System-on-Chip (SoC) architectures in meeting the control demands associated with performing quantum gates on trapped-ion qubits, particularly focusing on communication within the SoC. A principal focus of this paper is the data transfer latency and throughput of several high-speed on-chip mechanisms on Xilinx multi-processor SoCs, including those that utilize direct memory access (DMA). They are measured and evaluated to determine an upper bound on the time required to reconfigure a gate parameter. Worst-case and average-case bandwidth requirements for a custom gate sequencer core are compared with the experimental results. The lowest-variability, highest-throughput data-transfer mechanism is DMA between the real-time processing unit (RPU) and the PL, where bandwidths up to 19.2 GB/s are possible. For context, this enables reconfiguration of qubit gates in less than 2$\mu$s, comparable to the fastest gate time. Though this paper focuses on trapped-ion control systems, the gate abstraction scheme and measured communication rates are applicable to a broad range of quantum computing technologies.