Spike-based local synaptic plasticity: A survey of computational models and neuromorphic circuits

TL;DR

This survey reviews spike-based local synaptic plasticity models and neuromorphic circuits, highlighting their computational primitives, hardware mapping potential, and principles for efficient, low-power, on-chip learning.

Contribution

It provides a unified framework for comparing biological and neuromorphic models of synaptic plasticity, emphasizing their implementation in mixed-signal circuits.

Findings

Identification of computational primitives supporting low-latency hardware

Comparison of models within a common framework

Description of mixed-signal circuits enabling online learning

Abstract

Understanding how biological neural networks carry out learning using spike-based local plasticity mechanisms can lead to the development of powerful, energy-efficient, and adaptive neuromorphic processing systems. A large number of spike-based learning models have recently been proposed following different approaches. However, it is difficult to assess if and how they could be mapped onto neuromorphic hardware, and to compare their features and ease of implementation. To this end, in this survey, we provide a comprehensive overview of representative brain-inspired synaptic plasticity models and mixed-signal CMOS neuromorphic circuits within a unified framework. We review historical, bottom-up, and top-down approaches to modeling synaptic plasticity, and we identify computational primitives that can support low-latency and low-power hardware implementations of spike-based learning rules. We provide a common definition of a locality principle based on pre- and post-synaptic neuron information, which we propose as a fundamental requirement for physical implementations of synaptic plasticity. Based on this principle, we compare the properties of these models within the same framework, and describe the mixed-signal electronic circuits that implement their computing primitives, pointing out how these building blocks enable efficient on-chip and online learning in neuromorphic processing systems.