Timespot1: A 28nm CMOS Pixel Read-Out ASIC for 4D Tracking at High Rates

TL;DR

Timespot1 is a CMOS 28 nm ASIC with a 32x32 pixel matrix designed for high-rate, high-precision 4D tracking in collider experiments, achieving sub-50 ps timing resolution and handling hundreds of kHz per pixel.

Contribution

This paper introduces the first characterization of Timespot1, a novel small-size ASIC with integrated TDCs for high-rate, high-precision 4D tracking in collider environments.

Findings

Time resolution below 50 ps RMS achieved

Maximum readout rate of 3 MHz per pixel

Power consumption kept below 40 μW per pixel

Abstract

We present the first characterization results of Timespot1, an ASIC designed in CMOS 28 nm technology, featuring a $32 \times 32$ pixel matrix with a pitch of $55 ~ \mu m$. Timespot1 is the first small-size prototype, conceived to readout fine-pitch pixels with single-hit time resolution below $50 ~ ps_\text{rms}$ and input rates of several hundreds of kilohertz per pixel. Such experimental conditions will be typical of the next generation of high-luminosity collider experiments, from the LHC run5 and beyond. Each pixel of the ASIC includes a charge amplifier, a discriminator, and a Time-to-Digital Converter with time resolution indicatively of $22.6 ~ ps_\text{rms}$ and maximum readout rates (per pixel) of $3 ~ MHz$. To respect system-level constraints, the timing performance has been obtained keeping the power budget per pixel below $40 ~ \mu W$. The ASIC has been tested and characterised in the laboratory concerning its performance in terms of time resolution, power budget and sustainable rates. The ASIC will be hybridized on a matched $32 \times 32$ pixel sensor matrix and will be tested under laser beam and Minimum Ionizing Particles in the laboratory and at test beams. In this paper we present a description of the ASIC operation and the first results obtained from characterization tests concerning its performance.