Evaluating the effects of reducing voltage margins for energy-efficient operation of MPSoCs

TL;DR

This paper investigates reducing voltage guardbands in MPSoCs to improve energy efficiency, demonstrating up to 27% energy savings by intentionally violating manufacturer-defined margins while maintaining system reliability through error detection.

Contribution

It provides a practical assessment of voltage margin reduction on a commercial RISC-V MPSoC and explores error detection techniques to sustain reliability with lower guardbands.

Findings

Achieved up to 27% energy reduction by reducing voltage margins.

Validated that error detection can mitigate errors from aggressive voltage reduction.

Identified feasible voltage margin violations without compromising system correctness.

Abstract

Voltage margins, or guardbands, are imposed on DVFS systems to account for process, voltage, and temperature variability effects. While necessary to assure correctness, guardbands reduce energy efficiency, a crucial requirement for embedded systems. The literature shows that error detection techniques can be used to maintain the system's reliability while reducing or eliminating the guardbands. This letter assesses the practically available margins of a commercial RISC-V MPSoC while violating its guardband limits. The primary motivation of this work is to support the development of an efficient system leveraging the redundancy of multicore architectures for an error detection and correction scheme capable of mitigating the errors caused by aggressive voltage margin reduction. For an equivalent performance, we achieved up to 27% energy reduction while violating the manufacturer's defined guardband, leaving reasonable energy margins for further development.