Scalable Damper-based Deterministic Networking

TL;DR

This paper introduces a scalable Damper-based architecture for large-scale deterministic IP networks, ensuring end-to-end delay and jitter guarantees suitable for 5G, with an efficient control plane for admission control and routing.

Contribution

It extends the LDN architecture by incorporating dampers to relax clock synchronization needs and proposes a column generation algorithm for efficient admission control.

Findings

The architecture meets delay and jitter guarantees in simulation.

The control plane efficiently manages large-scale network flows.

The Damper-based approach reduces synchronization requirements.

Abstract

With 5G networking, deterministic guarantees are emerging as a key enabler. In this context, we present a scalable Damper-based architecture for Large-scale Deterministic IP Networks (D-LDN) that meets required bounds on end-to-end delay and jitter. This work extends the original LDN architecture, where flows are shaped at ingress gateways and scheduled for transmission at each link using an asynchronous and cyclic opening of gate-controlled queues. To further relax the need for clock synchronization between devices, we use dampers, that consist in jitter regulators, to control the burstiness flows to provide a constant target delay at each hop. We introduce in details how data plane functionalities are implemented at all nodes (gateways and core) and we derive how the end-to-end delay and jitter are calculated. For the control plane, we propose a column generation algorithm to quickly take admission control decisions and maximize the accepted throughput. For a set of flows, it determines acceptance and selects the best shaping and routing policy. Through a proof-of-concept implementation in simulation, we verify that the architecture meets promised guarantees and that the control plane can operate efficiently at large-scale.