A Novel Non-Volatile Inverter-based CiM: Continuous Sign Weight Transition and Low Power on-Chip Training

TL;DR

This paper introduces a novel ferroelectric inverter design for non-volatile, low-power, high-speed on-chip training in computing-in-memory systems, enabling continuous weight transition without off-chip assistance.

Contribution

The work presents a new 1T1I ferroelectric inverter design that achieves continuous weight transition and low power consumption for on-chip training, improving upon existing methods.

Findings

Successful demonstration of non-volatile inverter with ferroelectric HfO2.

Pure on-chip weight transition at optimized current levels.

Potential for further improvements with a 2T1I design.

Abstract

In this work, we report a novel design, one-transistor-one-inverter (1T1I), to satisfy high speed and low power on-chip training requirements. By leveraging doped HfO2 with ferroelectricity, a non-volatile inverter is successfully demonstrated, enabling desired continuous weight transition between negative and positive via the programmable threshold voltage (VTH) of ferroelectric field-effect transistors (FeFETs). Compared with commonly used designs with the similar function, 1T1I uniquely achieves pure on-chip-based weight transition at an optimized working current without relying on assistance from off-chip calculation units for signed-weight comparison, facilitating high-speed training at low power consumption. Further improvements in linearity and training speed can be obtained via a two-transistor-one-inverter (2T1I) design. Overall, focusing on energy and time efficiencies, this work provides a valuable design strategy for future FeFET-based computing-in-memory (CiM).