Valley-Spin Hall Effect-based Nonvolatile Memory with Exchange-Coupling-Enabled Electrical Isolation of Read and Write Paths

TL;DR

This paper introduces a VSH-based MRAM design that electrically isolates read and write paths using exchange-coupled magnets, reducing read resistance and improving read performance while maintaining compactness.

Contribution

It proposes a novel VSH-MRAM architecture with exchange-coupled magnets for electrical isolation, enhancing read speed and energy efficiency over existing designs.

Findings

39%-42% reduction in read time

36%-46% reduction in read energy

1.1X-1.3X larger sense margin

Abstract

Valley-spin hall (VSH) effect in monolayer WSe2 has been shown to exhibit highly beneficial features for nonvolatile memory (NVM) design. Key advantages of VSH-based magnetic random-access memory (VSH-MRAM) over spin orbit torque (SOT)-MRAM include access transistor-less compact bit-cell and low power switching of perpendicular magnetic anisotropy (PMA) magnets. Nevertheless, large device resistance in the read path (RS) due to low mobility of WSe2 and Schottky contacts deteriorates sense margin, offsetting the benefits of VSH-MRAM. To address this limitation, we propose another flavor of VSH-based MRAM that (while inheriting most of the benefits of VSH-MRAM) achieves lower RS in the read path by electrically isolating the read and write terminals. This is enabled by coupling VSH with electrically-isolated but magnetically-coupled PMA magnets via interlayer exchange-coupling. Designing the proposed devices using object oriented micro magnetic framework (OOMMF) simulation, we ensure the robustness of the exchange-coupled PMA system under process variations. To maintain a compact memory footprint, we share the read access transistor across multiple bit-cells. Compared to the existing VSH-MRAMs, our design achieves 39%-42% and 36%-46% reduction in read time and energy, respectively, along with 1.1X-1.3X larger sense margin at a comparable area. This comes at the cost of 1.7X and 2.0X increase in write time and energy, respectively. Thus, the proposed design is suitable for applications in which reads are more dominant than writes.