Mining SoC Message Flows with Attention Model
Md Rubel Ahmed, Bardia Nadimi, Hao Zheng

TL;DR
This paper introduces a deep learning approach using attention models to automatically infer accurate system-level message flow specifications from complex SoC communication traces, improving over existing tools.
Contribution
The paper presents a novel attention-based deep sequence modeling method for mining SoC message flows, addressing complexity challenges in concurrent traces.
Findings
Outperforms existing trace mining tools on five concurrent traces
Effectively handles complexity of concurrent SoC communication traces
Demonstrates significant accuracy improvements over prior methods
Abstract
High-quality system-level message flow specifications are necessary for comprehensive validation of system-on-chip (SoC) designs. However, manual development and maintenance of such specifications are daunting tasks. We propose a disruptive method that utilizes deep sequence modeling with the attention mechanism to infer accurate flow specifications from SoC communication traces. The proposed method can overcome the inherent complexity of SoC traces induced by the concurrent executions of SoC designs that existing mining tools often find extremely challenging. We conduct experiments on five highly concurrent traces and find that the proposed approach outperforms several existing state-of-the-art trace mining tools.
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Taxonomy
TopicsVLSI and Analog Circuit Testing · Software Testing and Debugging Techniques · Formal Methods in Verification
