Operation and Design of Ferroelectric FETs for a BEOL Compatible Device Implementation

TL;DR

This paper investigates the operation and design of ferroelectric FETs (FeFETs) through numerical simulations and experimental data analysis, emphasizing charge trapping effects and design parameters to optimize device performance.

Contribution

It introduces a comprehensive analysis of charge trapping in FeFETs and explores design options affecting memory window and resistance states, advancing BEOL compatible device development.

Findings

Charge trapping is crucial for matching simulations with experimental hysteresis.

Channel thickness and doping influence the memory window and resistance states.

Proper design can optimize FeFET performance for BEOL integration.

Abstract

We present a study based on numerical simulations and comparative analysis of recent experimental data concerning the operation and design of FeFETs. Our results show that a proper consideration of charge trapping in the ferroelectric-dielectric stack is indispensable to reconcile simulations with experiments, and to attain the desired hysteretic behavior of the current-voltage characteristics. Then we analyze a few design options for polysilicon channel FeFETs and, in particular, we study the influence of the channel thickness and doping concentration on the memory window, and on the ratio between the polarization dependent, high and low resistance state.