SMART: Investigating the Impact of Threshold Voltage Suppression in an In-SRAM Multiplication/Accumulation Accelerator for Accuracy Improvement in 65 nm CMOS Technology

TL;DR

This paper introduces SMART, a technique that suppresses threshold voltage in In-SRAM MAC accelerators to enhance accuracy in 65nm CMOS technology, demonstrating improved precision with low power consumption.

Contribution

The paper presents a novel threshold voltage suppression method for In-SRAM MAC accelerators, improving accuracy and efficiency in 65nm CMOS technology.

Findings

Enhanced MAC accuracy with less than 0.009 standard deviations.

Achieved 0.683 pJ energy per computation at 1V supply.

Validated effectiveness through analytical and Monte-Carlo simulations.

Abstract

State-of-the-art in-memory computation has recently emerged as the most promising solution to overcome design challenges related to data movement inside current computing systems. One of the approaches to performing in-memory computation is based on the analog behavior of the data stored inside the memory cell. These approaches proposed various system architectures for that. In this paper, we investigated the effect of threshold voltage suppression on the access transistors of the In-SRAM multiplication and accumulation (MAC) accelerator to improve and enhance the performance of bit line (bit line bar) discharge rate that will increase the accuracy of MAC operation. We provide a comprehensive analytical analysis followed by circuit implementation, including a Monte-Carlo simulation by a 65nm CMOS technology. We confirmed the efficiency of our method (SMART) for a four-by-four-bit MAC operation. The proposed technique improves the accuracy while consuming 0.683 pJ per computation from a power supply of 1V. Our novel technique presents less than 0.009 standard deviations for the worst-case incorrect output scenario.