Zydeco-Style Spike Sorting Low Power VLSI Architecture for IoT BCI Implants

TL;DR

This paper introduces a low-power, simplified VLSI architecture called Zydeco-Style for spike sorting in brain-computer interfaces, aiming to improve power efficiency, accuracy, and safety for implantable IoT devices.

Contribution

The paper presents a novel low-power VLSI architecture for spike sorting that is computationally simpler and more accurate than existing solutions, suitable for implantable BCI devices.

Findings

Achieves up to 93.5% accuracy in worst-case scenarios

Reduces power consumption and heat dissipation in implantable BCIs

Demonstrates feasibility through Verilog simulation and conceptual design

Abstract

Brain Computer Interface (BCI) has great potential for solving many brain signal analysis limitations, mental disorder resolutions, and restoring missing limb functionality via neural-controlled implants. However, there is no single available, and safe implant for daily life usage exists yet. Most of the proposed implants have several implementation issues, such as infection hazards and heat dissipation, which limits their usability and makes it more challenging to pass regulations and quality control production. The wireless implant does not require a chronic wound in the skull. However, the current complex clustering neuron identification algorithms inside the implant chip consume a lot of power and bandwidth, causing higher heat dissipation issues and draining the implant's battery. The spike sorting is the core unit of an invasive BCI chip, which plays a significant role in power consumption, accuracy, and area. Therefore, in this study, we propose a low-power adaptive simplified VLSI architecture, "Zydeco-Style," for BCI spike sorting that is computationally less complex with higher accuracy that performs up to 93.5% in the worst-case scenario. The architecture uses a low-power Bluetooth Wireless communication module with external IoT medical ICU devices. The proposed architecture was implemented and simulated in Verilog. In addition, we are proposing an implant conceptual design.