FPGA Random Number Generator

TL;DR

This paper presents a Verilog-based FPGA design that generates 32-bit random numbers in a single clock cycle using measurement and scrambling algorithms, suitable for encryption, statistical, and gaming applications.

Contribution

It introduces a novel hardware implementation of a high-speed random number generator using measurement and scrambling algorithms on FPGA.

Findings

Generates 32-bit random numbers in one clock cycle.

Uses measurement and scrambling algorithms for randomness.

Proof-of-concept verified on FPGA hardware.

Abstract

Random number generation is a key technology that is useful in a variety of ways. Random numbers are often used to generate keys for data encryption. Random numbers generated at a sufficiently long length can encrypt sensitive data and make it difficult for another computer or person to decrypt the data. Other uses for random numbers include statistical sampling, search/sort algorithms, gaming, and gambling. Due to the wide array of applications for random numbers, it would be useful to create a method of generating random numbers reliably directly in hardware to generate a ready supply of a random number for whatever the end application may be. This paper offers a proof-of-concept for creating a verilog-based hardware design that utilizes random measurement and scrambling algorithms to generate 32-bit random synchronously with a single clock cycle on a field-programmable-gate-array(FPGA).