Hardware-Software Co-Design of BIKE with HLS-Generated Accelerators

TL;DR

This paper presents a hardware-software co-design approach for BIKE, a post-quantum cryptosystem, using HLS-generated accelerators on embedded CPU-FPGA platforms, achieving significant speedups.

Contribution

It introduces a novel co-design methodology for BIKE on heterogeneous embedded platforms with HLS-based FPGA accelerators, focusing on small FPGAs for improved performance.

Findings

Achieved up to 2.78x speedup on Z-7020 FPGA.

Demonstrated effective hardware-software integration for post-quantum cryptography.

Targeted small FPGAs for embedded systems, contrasting with performance-optimized solutions.

Abstract

In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize post-quantum cryptosystems, aiming to assess their security and speed up their adoption in production scenarios. Several hardware and software implementations have been proposed for each candidate, while only a few target heterogeneous platforms featuring CPUs and FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to timely deliver the hardware accelerators. In contrast to state-of-the-art solutions targeting performance-optimized HLS accelerators, the proposed solution targets the small FPGAs implemented in the heterogeneous platforms for embedded systems. Compared to the software-only execution of BIKE, the experimental results collected on the systems-on-chip of the entire Xilinx Zynq-7000 family highlight a performance speedup ranging from 1.37x, on Z-7010, to 2.78x, on Z-7020.