Hardware-Conscious Optimization of the Quantum Toffoli Gate

TL;DR

This paper introduces a hybrid analytical and numerical approach to optimize Toffoli gates at the native gate level for superconducting qubit hardware, reducing infidelity and gate count.

Contribution

It presents a novel method combining analytical native gate optimization with numerical techniques, specifically applied to Toffoli gates on IBMQ hardware, generalizable to other gates and architectures.

Findings

18% reduction in infidelity on IBM Jakarta

Toffoli gate implementation with 6 multi-qubit gates

25% reduction in multi-qubit gates compared to canonical implementation

Abstract

While quantum computing holds great potential in combinatorial optimization, electronic structure calculation, and number theory, the current era of quantum computing is limited by noisy hardware. Many quantum compilation approaches can mitigate the effects of imperfect hardware by optimizing quantum circuits for objectives such as critical path length. Few approaches consider quantum circuits in terms of the set of vendor-calibrated operations (i.e., native gates) available on target hardware. This manuscript expands the analytical and numerical approaches for optimizing quantum circuits at this abstraction level. We present a procedure for combining the strengths of analytical native gate-level optimization with numerical optimization. Although we focus on optimizing Toffoli gates on the IBMQ native gate set, the methods presented are generalizable to any gate and superconducting qubit architecture. Our optimized Toffoli gate implementation demonstrates an $18\%$ reduction in infidelity compared with the canonical implementation as benchmarked on IBM Jakarta with quantum process tomography. Assuming the inclusion of multi-qubit cross-resonance (MCR) gates in the IBMQ native gate set, we produce Toffoli implementations with only six multi-qubit gates, a $25\%$ reduction from the canonical eight multi-qubit implementations for linearly connected qubits.