Hardware Software Co-design of Statistical and Deep Learning Frameworks for Wideband Sensing on Zynq System on Chip

TL;DR

This paper presents a hardware-software co-design approach on Zynq SoC for efficient spectrum sensing using sub-Nyquist sampling, orthogonal matching pursuit, and deep learning architectures to improve performance and resource utilization.

Contribution

It introduces a novel mapping of OMP and deep learning algorithms on Zynq SoC for wideband spectrum sensing, addressing performance and prior knowledge challenges.

Findings

OMP performance degrades for sparse spectrum

Deep learning architectures improve spectrum reconstruction

Hardware-software co-design optimizes resource and power use

Abstract

With the introduction of spectrum sharing and heterogeneous services in next-generation networks, the base stations need to sense the wideband spectrum and identify the spectrum resources to meet the quality-of-service, bandwidth, and latency constraints. Sub-Nyquist sampling (SNS) enables digitization for sparse wideband spectrum without needing Nyquist speed analog-to-digital converters. However, SNS demands additional signal processing algorithms for spectrum reconstruction, such as the well-known orthogonal matching pursuit (OMP) algorithm. OMP is also widely used in other compressed sensing applications. The first contribution of this work is efficiently mapping the OMP algorithm on the Zynq system-on-chip (ZSoC) consisting of an ARM processor and FPGA. Experimental analysis shows a significant degradation in OMP performance for sparse spectrum. Also, OMP needs prior knowledge of spectrum sparsity. We address these challenges via deep-learning-based architectures and efficiently map them on the ZSoC platform as second contribution. Via hardware-software co-design, different versions of the proposed architecture obtained by partitioning between software (ARM processor) and hardware (FPGA) are considered. The resource, power, and execution time comparisons for given memory constraints and a wide range of word lengths are presented for these architectures.