Performance of the Vipera framework for DSLs on micro-core architectures

TL;DR

This paper evaluates the Vipera framework's effectiveness in generating efficient, compact code for dynamic DSLs on micro-core architectures, focusing on performance and size.

Contribution

It provides an empirical analysis of Vipera's performance and code size, highlighting its suitability for micro-core architectures.

Findings

Vipera produces optimized code with acceptable performance.

Code size remains within practical limits for micro-core devices.

Performance varies depending on the specific DSL and application.

Abstract

Vipera provides a compiler and runtime framework for implementing dynamic Domain-Specific Languages on micro-core architectures. The performance and code size of the generated code is critical on these architectures. In this paper we present the results of our investigations into the efficiency of Vipera in terms of code performance and size.