Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters

TL;DR

This paper investigates the physical implementation flexibility of high-performance processing clusters, proposing a hierarchical modeling approach with soft tiles to optimize die utilization in scalable accelerators.

Contribution

It introduces a methodology to model clusters as soft tiles, enhancing flexibility and utilization in the physical design of high-performance computing architectures.

Findings

Flexibility range for RISC-V core clusters established

Hierarchical implementation methodology proposed

Potential for improved die utilization demonstrated

Abstract

Modern high-performance computing architectures (Multicore, GPU, Manycore) are based on tightly-coupled clusters of processing elements, physically implemented as rectangular tiles. Their size and aspect ratio strongly impact the achievable operating frequency and energy efficiency, but they should be as flexible as possible to achieve a high utilization for the top-level die floorplan. In this paper, we explore the flexibility range for a high-performance cluster of RISC-V cores with shared L1 memory used to build scalable accelerators, with the goal of establishing a hierarchical implementation methodology where clusters can be modeled as soft tiles to achieve optimal die utilization.