Integral Sampler and Polynomial Multiplication Architecture for Lattice-based Cryptography

TL;DR

This paper introduces an integrated architecture for lattice-based cryptography samplers that reduces resource consumption by reusing computational units, enhancing hardware efficiency against quantum threats.

Contribution

It presents a novel integral architecture for samplers in lattice cryptography, optimizing resource usage during polynomial multiplication.

Findings

Reduces DSP usage in discrete Ziggurat sampling

Reuses multipliers and adders for efficiency

Improves hardware resource management

Abstract

With the surge of the powerful quantum computer, lattice-based cryptography proliferated the latest cryptography hardware implementation due to its resistance against quantum computers. Among the computational blocks of lattice-based cryptography, the random errors produced by the sampler play a key role in ensuring the security of these schemes. This paper proposes an integral architecture for the sampler, which can reduce the overall resource consumption by reusing the multipliers and adders within the modular polynomial computation. For instance, our experimental results show that the proposed design can effectively reduce the discrete Ziggurat sampling method in DSP usage.