{\AE}r{\o}: A Platform Architecture for Mixed-Criticality Airborne Systems
Shibarchi Majumder, Jens Frederik Dalsgaard Nielsen, Thomas Bak

TL;DR
This paper introduces a hardware-based platform architecture for mixed-criticality airborne systems, using processor partitions and cycle-accurate scheduling to improve isolation, predictability, and reduce overhead in real-time embedded applications.
Contribution
It presents a novel hardware-level partitioning approach with a pipelined processor and cycle-accurate scheduling for mixed-criticality systems, demonstrated on FPGA for avionics.
Findings
Hardware partitioning improves isolation and predictability.
Cycle-accurate scheduling accommodates diverse application requirements.
Implementation on FPGA validates the approach in avionics use case.
Abstract
Real-time embedded platforms with resource constraints can take the benefits of mixed-criticality system where applications with different criticality-level share computational resources, with isolation in the temporal and spatial domain. A conventional software-based isolation mechanism adds additional overhead and requires certification with the highest level of criticality present in the system, which is often an expensive process. In this article, we present a different approach where the required isolation is established at the hardware-level by featuring partitions within the processor. A four-stage pipelined soft-processor with replicated resources in the data-path is introduced to establish isolation and avert interference between the partitions. A cycle-accurate scheduling mechanism is implemented in the hardware for hard-real-time partition scheduling that can accommodate…
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