An Accurate and Hardware-Efficient Dual Spike Detector for Implantable Neural Interfaces

TL;DR

This paper presents a novel dual-detector hardware architecture for implantable neural interfaces that achieves high spike detection accuracy with significantly reduced power consumption and area, suitable for low-power brain-machine interfaces.

Contribution

The paper introduces a dual-detector architecture with adaptive threshold estimation that improves hardware efficiency and detection accuracy for implantable neural spike detection.

Findings

Achieved 98.9% detection accuracy on Wave Clus dataset.

Reduced power consumption by 39.7% compared to state-of-the-art.

Reduced area by 78.8% compared to previous designs.

Abstract

Spike detection plays a central role in neural data processing and brain-machine interfaces (BMIs). A challenge for future-generation implantable BMIs is to build a spike detector that features both low hardware cost and high performance. In this work, we propose a novel hardware-efficient and high-performance spike detector for implantable BMIs. The proposed design is based on a dual-detector architecture with adaptive threshold estimation. The dual-detector comprises two separate TEO-based detectors that distinguish a spike occurrence based on its discriminating features in both high and low noise scenarios. We evaluated the proposed spike detection algorithm on the Wave Clus dataset. It achieved an average detection accuracy of 98.9%, and over 95% in high-noise scenarios, ensuring the reliability of our method. When realized in hardware with a sampling rate of 16kHz and 7-bits resolution, the detection accuracy is 97.4%. Designed in 65nm TSMC process, a 256-channel detector based on this architecture occupies only 682$\mu m^2$ /Channel and consumes 0.07$\mu$W/Channel, improving over the state-of-the-art spike detectors by 39.7% in power consumption and 78.8% in area, while maintaining a high accuracy.