Scalable Nanophotonic-Electronic Spiking Neural Networks

TL;DR

This paper presents a scalable nanophotonic-electronic spiking neural network architecture using co-integrated CMOS and silicon photonics, demonstrating novel neuron designs and on-chip learning algorithms with promising results.

Contribution

It introduces a monolithic silicon photonics neuron circuit and explores on-chip learning algorithms like RPB and CHL for scalable SNNs.

Findings

Successfully simulated a silicon photonics neuron with advanced spiking behaviors.

Demonstrated on-chip Random Backpropagation matching linear regression performance.

Applied Contrastive Hebbian Learning to MZI mesh networks with improved task performance.

Abstract

Spiking neural networks (SNN) provide a new computational paradigm capable of highly parallelized, real-time processing. Photonic devices are ideal for the design of high-bandwidth, parallel architectures matching the SNN computational paradigm. Co-integration of CMOS and photonic elements allow low-loss photonic devices to be combined with analog electronics for greater flexibility of nonlinear computational elements. As such, we designed and simulated an optoelectronic spiking neuron circuit on a monolithic silicon photonics (SiPh) process that replicates useful spiking behaviors beyond the leaky integrate-and-fire (LIF). Additionally, we explored two learning algorithms with the potential for on-chip learning using Mach-Zehnder Interferometric (MZI) meshes as synaptic interconnects. A variation of Random Backpropagation (RPB) was experimentally demonstrated on-chip and matched the performance of a standard linear regression on a simple classification task. Meanwhile, the Contrastive Hebbian Learning (CHL) rule was applied to a simulated neural network composed of MZI meshes for a random input-output mapping task. The CHL-trained MZI network performed better than random guessing but does not match the performance of the ideal neural network (without the constraints imposed by the MZI meshes). Through these efforts, we demonstrate that co-integrated CMOS and SiPh technologies are well-suited to the design of scalable SNN computing architectures.